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preliminary w49f002a 256k 8 cmos flash memory publication release date: september 12, 2001 - 1 - revision a1 general description the w49f002a is a 2 - megabit, 5 - volt only cmos flash memory organized as 256k 8 bits. the device can be programmed and erased in - system with a standard 5v power supply. a 12 - volt v pp is not required. the unique cell architecture of the w49f002a results in fast program/erase operations with extremely low current consumption (compared to other comparable 5 - volt flash memory products). the device can also be programmed and erased using standard eprom programmers. features single 5 - volt operations: - 5 - volt read - 5 - volt erase - 5 - volt program fast program operation: - byte - by - byte programming: 35 m s (typ.) fast erase operation: 100 ms (ty p.) fast read access time: 120 ns ten - year data retention hardware data protection one 16k byte boot block with lockout pro tection typical page write (erase/program) cycles: 10 - 100 two 8k byte parameter blocks two main memory blocks (96k, 128k) bytes low power consumption - active current: 25 ma (typ.) - standby current: 20 m a (typ.) automatic program and erase timing with internal v pp generation end of program or erase detecti on - toggle bit - data polling latched address and data ttl compatible i/o jedec standard byte - wide pinouts available pack ages: 32 - pin dip and plcc
preliminary w49f002a - 2 - pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq0 dq1 dq2 vss a7 a6 a5 a4 a3 a2 a1 a0 a16 a15 a12 v #we a14 a13 a8 a9 a11 #oe a10 #ce dq7 dq6 dq5 dq4 dq3 dd a17 32-pin dip #reset 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 d q 2 v s s d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 #oe a10 #ce dq7 a 1 2 a 1 6 v d d # w e a 1 5 32-pin plcc a 1 7 # r e s e t block diagram control output buffer decoder #ce #oe #we a0 . . a17 . . dq0 v dd v ss dq7 3ffff 20000 1ffff 38000 37fff 3a000 39fff 00000 3c000 3bfff parameter block2 8k bytes boot block 16k bytes parameter block1 8k bytes #reset main memory block2 128k bytes main memory block1 96k bytes pin description symbol pin name #reset reset a0 - a17 address inputs dq0 - dq7 data inputs/outputs #ce chip enable #oe outpu t enable #we write enable v dd power supply v ss ground
preliminary w49f002a publication release date: september 12, 2001 - 3 - revision a1 functional descripti on device operation read mode the read operation of the w49f002a is controlled by #ce and #oe, both of which have to be low for the host to obtain data from the outputs. #ce i s used for device selection. when #ce is high, the chip is de - selected and only standby power will be consumed. #oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either #ce or #oe is high. refer to the timing waveforms for details. write mode device erase and program are accomplished via the command register. the content of the register serves as inputs to the internal state machine. the state machine outputs dictate the function of the dev ice. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written to bring #we to logic low state when #ce is at logic low state and #oe is at logic high state. addresses are latched on the falling edge of #we or #ce, whichever happens later; while data is latched on the rising edge of #we or #ce, whichever happens first. standard micr oprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. standby mode there are two ways to implement the standby mode on the w49f002a device, both using the #ce pin. a cmos st andby mode is achieved with the #ce input held at v dd - 0.3v. under this condition the current is typically reduced to less than 100 m a. a ttl standby mode is achieved with the #ce pin held at v ih . under this condition the current is typically reduced to l ess than 3 ma. in the standby mode the outputs are in the high impedance state, independent of the #oe input. output disable mode with the #oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. auto - select mode the auto - select mode allows the reading of a binary code from the device and will identify its manufacturer and type. this mode is intended to be used by programming equipment for the purpose of automatically matchin g the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5v to 12.5v) on address pin a9. two ide ntifier bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all addresses are don t cares except a0 and a1 (see "auto - select codes").
preliminary w49f002a - 4 - the manufacturer and device codes may also be read via the command register; i.e., the w49f002a is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in "auto - select codes". byte 0 (a0 = v il ) represents the manufacturer s code (winbond = dah) and byte 1 (a0 = v ih ) the devic e identifier code ( w49f002a = 0bh). all identifiers for manufacturer and device will exhibit odd parity with dq7 defined as the parity bit. in order to read the proper device codes when executing the auto - select, a1 must be v il . reset mode: hardware reset the #reset pin provides a hardware method of resetting the device to reading array data. when the system drives the #reset pin low for at least a period of t rp , the device immediately terminates any operation in progress, tri - states all data output pins, a nd ignores all read/write attempts for the duration of the #reset pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command se quence, to ensure data integrity. current is reduced for the duration of the #reset pulse. when #reset is held at v il , the device enters the ttl standby mode; if #reset is held at v ss , the device enters the cmos standby mode. the #reset pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot - up firmware from the flash memory. data protection the w49f002a is designed to offer protection against accidental erasure or programmin g caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi - bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v dd power - up and power - down transitions or system noise. low v dd write i nhibit to avoid initiation of a write cycle during v dd power - up and power - down, the w49f002a locks out write cycles for v dd < 2.5v. when v dd < 2.5v, all internal program/erase circuits are disabled, and the device resets to the read mode. the w49f002a igno res all writes until v dd > 2.5v. the user must ensure that the control pins are in the correct logic state when v dd > 2.5v to prevent unintentional writes. write pulse "glitch" protection noise pulses of less than 10 ns (typical) on #oe, #oe, or #we will n ot initiate a write cycle. logical inhibit writing is inhibited by holding any one of #oe = v il , #ce = v ih , or #we = v ih . to initiate a write cycle #ce and #we must be a logical zero while #oe is a logical one. power - up write inhibit power - up of the device with #we = #ce = v il and #oe = v ih will not accept commands on the rising edge of #we. the internal state machine is automatically reset to the read mode on power - up.
preliminary w49f002a publication release date: september 12, 2001 - 5 - revision a1 command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "command definitions" defines the valid register command sequences. moreover, both reset/read co mmands are functionally equivalent, resetting the device to the read mode. read command the device will automatically power - up in the read state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrie ve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. the device will automatically returns to read state after completing an embedded program or embedded erase algorithm. refer to the ac read characteristics and waveforms for the specific timing parameters. auto - select command flash memories are intended for use in applications where the local cpu can alter memory contents. as such, manufacture and device codes must be accessible wh ile the device resides in the target system. prom programmers typically access the signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally a desirable system design practice. the device co ntains an auto - select command operation to supplement traditional prom programming methodology. the operation is initiated by writing the auto - select command sequence into the command register. following the command write, a read cycle from address xx00h r etrieves the manufacture code of dah. a read cycle from address xx01h returns the device code ( w49f002a = 0bh). byte program command the device is programmed on a byte - by - byte basis. programming is a four - bus - cycle operation. the program command sequence i s initiated by writing two "unlock" write cycles, followed by the program set - up command. the program address and data are written next, which in turn initiate the embedded program algorithm. addresses are latched on the falling edge of #ce or #we, whichev er happens later and the data is latched on the rising edge of #ce or #we, whichever happens first. the rising edge of #ce or #we (whichever happens first) begins programming using the embedded program algorithm. upon executing the algorithm, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq7 (also use d as data polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "hardware sequence flags"). therefore, the device requires that a valid address to the device be sup plied by the system at this particular instance of time for data polling operations. data polling must be performed at the memory location which is being programmed.
preliminary w49f002a - 6 - any commands written to the chip during the embedded program algorithm will be ignored. if a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. programming is allowed in any sequence and across sector boundaries. beware that a data "0" cannot be programmed back to a "1". only erase op erations can convert "0"s to "1"s. refer to the embedded programming algorithm using typical command strings and bus operations. chip erase command chip erase is a six - bus - cycle operation. there are two "unlock" write cycles. these are followed by writing the "set - up" command. two more "unlock" write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automa tically erase and verify the entire memory for an all one data pattern. the erase is performed sequentially on each sector at the same time (see "feature"). the system is not required to provide any controls or timings during these operations. the automati c erase begins on the rising edge of the last #we pulse in the command sequence and terminates when the data on dq7 is "1" at which time the device returns to read the mode. refer to the embedded erase algorithm using typical command strings and bus operat ions. sector erase command sector erase is a six bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set - up" command. two more "unlock" write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of #we, while the command (30h) is latched on the rising edge of #we. sector erase does not require the user to program the device prior to erase. when erasing a sector or sec tors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the rising edge of the #we pulse for the last sector erase command pulse and terminates when the data on dq7, data polling, is "1." refer to the embedded erase algorithm using typical command strings and bus operations. write operation status dq7: data polling the w49f002a device features data polling as a method to indicate t o the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq7. upon completion of the embedded program algorithm, an a ttempt to read the device will produce the true data last written to dq7. during the embedded erase algorithm, an attempt to read the device will produce a "0" at the dq7 output. upon completion of the embedded erase algorithm, an attempt to read the devi ce will produce a "1" at the dq7 output. the flowchart for data polling (dq7) is shown in "data polling algorithm".
preliminary w49f002a publication release date: september 12, 2001 - 7 - revision a1 for chip erase, the data polling is valid after the rising edge of the sixth pulse in the six #we write pulse sequence. for sector erase, th e data polling is valid after the last rising edge of the sector erase #we pulse. just prior to the completion of embedded algorithm operations dq7 may change asynchronously while the output enable (#oe) is asserted low. this means that the device is driv ing status information on dq7 at one instant of time and then that byte s valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algor ithm operations and dq7 has a valid data, the data outputs on dq0 ? dq6 may be still invalid. the valid data on dq0 - dq7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedde d erase algorithm, or sector erase time - out (see "command definitions"). see "#data polling during embedded algorithm timing diagrams". dq6: toggle bit the w49f002a also features the "toggle bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (#oe toggling) data from the device at any address will result in dq6 toggling between one and zero. once the embedded program or era se algorithm cycle is completed, dq6 will stop toggling and valid data will be read on the next successive attempt. during programming, the toggle bit is valid after the rising edge of the fourth #we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth #we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase #we pulse. the toggle bit is active during the sector erase time - out. table of operating m odes device bus operations mode pin #ce #oe #we #reset a0 - a17 dq0 - dq7 read v il v il v ih v ih ain dout write v il v ih v il v ih ain din write inhibit v ih x v il x x high z/dout v ih x x v ih x high z/dout standby v ih x x v ih x h igh z output disable v il v ih v ih v ih x high z reset x x x v il x high z
preliminary w49f002a - 8 - auto - select codes (high voltage method) description #ce #oe #we other add a9 a1 a0 dq7 to dq0 manufacturer id: winbond v il v il v ih x v id v il v il dah device id: w49f002a (top boo t block) v il v il v ih x v id v il v ih 0bh notes: 1. sa = sector address, x = don t care. sector protection verification: 01h (protected); 00h (unprotected). 2. the hardware sid read function is not included in all parts; please refer to ordering informatio n for details. hardware sequence flags operation dq7 dq6 (note*) embedded program algorithm #dq7 toggle standard mode embedded erase algorithm 0 toggle note*: dq7 require a valid address when reading status information. refer to the appropriate subs ection for further details. command defination (1) command no. of 1th cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle description cycles addr. data addr. data addr. data addr. data addr. data addr. data read 1 ain dout chip erase 6 5555 a a 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3) 30 byte program 4 5555 aa 2aaa 55 5555 a0 ain din boot block lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 notes: 1. address format: a14 - a0 (hex); data format: dq7 - dq0 (hex) 2. either one of the two product id exit commands can be used. 3. sa means: sector address if sa is within 3c000 to 3ffff (boot block address range), and the boot block programming lockout feature is activated, nothing will happen and the device will go back to read mode after 1 00 ns. if the boot block programming lockout feature is not activated, this command will erase boot block. if sa is within 3a000 to 3bfff (parameter block1 address range), this command will erase pb1. if sa is within 38000 to 39fff (parameter block2 addr ess range), this command will erase pb2. if sa is within 20000 to 37fff (main memory block1 address range), this command will erase mmb1. if sa is within 00000 to 1ffff (main memory block2 address range), this command will erase mmb2.
preliminary w49f002a publication release date: september 12, 2001 - 9 - revision a1 embedded algorith ms start write program command sequence (see below) increment address programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit last address ? no yes program command sequence (address/command): embedded programming algorithm
preliminary w49f002a - 10 - embedded algorithms, continued start write erase command sequence (see below) erasure completed 5555h/aah 5555h/aah 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 2aaah/55h 2aaah/55h 5555h/80h 5555h/80h sector address/30h 5555h/10h #data polling or toggle bit successfully completed chip erase command sequence (address/command): embedded erase algorithm individual sector erase command sequence (address/command):
preliminary w49f002a publication release date: september 12, 2001 - 11 - revision a1 embedded algorithms, continued start read byte (dq0-dq7) address = va pass dq7 = data ? yes no #data polling algorithm va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any sector group address during chip erase start read byte (dq0-dq7) address = don' t care dq6 = toggle ? yes no fail toggle bit algorithm
preliminary w49f002a - 12 - dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potent ial - 0.5 to +7.0 v operating temperature 0 to +70 c storage temperature - 65 to +150 c d.c. voltage on any pin to ground potential except a9 - 0.5 to v dd +1.0 v transient voltage (<20 ns) on any pin to ground potential - 1.0 to v dd +1.0 v voltage on a9 pin to ground potential - 0.5 to 12.5 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc operating characteristics (v dd = 5.0v 10 % , v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions limits unit min. typ. max. power supply current i cc #ce = #oe = v il , #we = v ih , all dqs open address inputs = v il /v ih , at f = 5 mhz - 25 50 ma standby v dd current (ttl input) i sb 1 #ce = v ih , all dqs open other inputs = v il /v ih - 2 3 ma standby v dd current (cmos input) i sb 2 #ce = v dd - 0.3v, all dqs open other inputs = v dd - 0.3v/ v ss - 20 100 m a input leakage current i li v in = v ss to v dd - - 10 m a output leakage current i lo v out = v ss to v dd - - 10 m a input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = - 0.4 ma 2.4 - - v
preliminary w49f002a publication release date: september 12, 2001 - 13 - revision a1 power - up timing parameter symbol typical unit power - up to read operation t pu . rea d 100 m s power - up to write operation t pu . write 5 ms capacitance (v dd = 5.0v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf ac characteristics ac test conditi ons parameter conditions input pulse levels 0v to 3v input rise/fall time <5 ns input/output timing level 1.5v / 1.5v output load 1 ttl gate and c l = 100 pf ac test load and waveform +5v 1.8k 1.3k d out w w (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output 100 pf
preliminary w49f002a - 14 - ac characteristics, continued read cycle timing parameters (v dd = 5.0v 10 % , v dd = 0v, t a = 0 to 70 c) parameter symbol min. max. unit read cycle time t rc 120 - ns chip enable access time t ce - 120 ns address access time t aa - 120 ns output enable access time t oe - 50 ns #ce low to active output t clz 0 - ns #oe low to active output t olz 0 - ns #ce high to high - z output t chz - 30 ns #oe high to high - z output t ohz - 30 ns output hold from address change t oh 0 - ns write cycle timing parameters parameter symbol min. typ. max. unit address setup time t as 0 - - ns address hold time t ah 50 - - ns #we and #ce setup time t cs 0 - - ns #we and #ce hold time t ch 0 - - ns #oe high setup time t oes 0 - - ns #oe high hold time t oeh 0 - - ns #ce pulse width t cp 100 - - ns #we pulse width t wp 100 - - ns #we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 10 - - ns byte programming time t bp - 35 50 m s erase cycle time t ec - 0.1 0.2 s note: all ac timing signals observe the following guidelines for determining setup and ho ld times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
preliminary w49f002a publication release date: september 12, 2001 - 15 - revision a1 ac characteristics, continued data polling and toggle bit timing parameters parameter symbol min. max. unit #oe to data polling output delay t oep - 50 ns #ce to data polling output delay t cep - 120 ns #oe to toggle bit output delay t oet - 50 ns #ce to toggle bit output delay t cet - 120 ns timing waveforms read cycle timing diagram address a17-0 dq7-0 data valid data valid high-z #ce #oe #we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z
preliminary w49f002a - 16 - timing waveforms, conti nued #we controlled command write cycle timing diagram address a17-0 dq7-0 data valid #ce #oe #we t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh #ce controlled command write cycle timing diagram high z data valid #ce #oe #we dq7-0 t as t ah t cph t oeh t dh t ds t cp t oes address a17-0
preliminary w49f002a publication release date: september 12, 2001 - 17 - revision a1 timing waveforms, continued program cycle timing diagram address a17-0 byte 0 byte 1 byte 2 internal write start dq7-0 #ce #oe #we byte program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 address data-in byte 3 #data polling timing diagram address a17-0 dq7 #we #oe #ce x x x x t cep t oeh t oep t oes t ec t bp or an an an an
preliminary w49f002a - 18 - timing waveforms, continued toggle bit timing diagram address a17-0 dq6 #ce #oe #we t oeh t oes t bp or t ec boot block lockout enable timing diagram sb2 sb1 sb0 address a17-0 dq7-0 #ce #oe #we sb3 sb4 sb5 six byte code for boot block lockout feature enable t ec t wp t wph 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 40
preliminary w49f002a publication release date: september 12, 2001 - 19 - revision a1 timing waveforms, continued chip erase timing diag ram sb2 sb1 sb0 address a17-0 dq7-0 #ce #oe #we sb3 sb4 sb5 internal erase starts six-byte code for 5v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10 sector erase timing diagram sb2 sb1 sb0 address a17-0 dq7-0 #ce #oe #we sb3 sb4 sb5 internal erase starts six-byte code for 5v-only software main memory erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa sa aa 55 80 aa 55 30 sa = sector address
preliminary w49f002a - 20 - ordering information part no. access time ( n s) power supply current max. ( m a) standby v dd current max. ( m a) cycling package w49f002a - 12 120 50 100 (cmos) 10 - 100 32 - pin dip w49f002ap - 12 120 50 100 (cmos) 10 - 100 32 - pin plcc notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. winbond offers top boot block device, if any of bottom boot block devices is required, please contact winbond faes.
preliminary w49f002a publication release date: september 12, 2001 - 21 - revision a1 package dimensions 32 - pin p - dip 1.dimensions d max. & s include mold flash or tie bar burrs. 2.dimension e1 does not include interlead flash. 3.dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6.general appearance spec. should be based on final visual inspection spec. . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4.dimension b1 does not include dambar 5.controlling dimension: inches 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 32 - pin plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.9 5 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.49 0 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.51 0 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
preliminary w49f002a - 22 - version history version date page description a1 sep. 12, 2001 - initial issued headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change without notice. headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798

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